\doxysection{RCC\+\_\+\+PLL3\+Init\+Type\+Def Struct Reference}
\hypertarget{struct_r_c_c___p_l_l3_init_type_def}{}\label{struct_r_c_c___p_l_l3_init_type_def}\index{RCC\_PLL3InitTypeDef@{RCC\_PLL3InitTypeDef}}


PLL3 Clock structure definition.  




{\ttfamily \#include $<$stm32h7xx\+\_\+hal\+\_\+rcc\+\_\+ex.\+h$>$}

\doxysubsubsection*{Public Attributes}
\begin{DoxyCompactItemize}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_r_c_c___p_l_l3_init_type_def_abf03c908c2a85af8a4e49f9988ad3a33}{PLL3M}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_r_c_c___p_l_l3_init_type_def_a5f97ae4e24ae3b2458e2420e15fc6a28}{PLL3N}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_r_c_c___p_l_l3_init_type_def_a9a1a667bbc487367b94bb798c51c7ed3}{PLL3P}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_r_c_c___p_l_l3_init_type_def_a0b26665402abcaa012598f506e1aeae0}{PLL3Q}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_r_c_c___p_l_l3_init_type_def_aad5f277a07cd7b0c045f336c8818b210}{PLL3R}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_r_c_c___p_l_l3_init_type_def_ab47e853e3c4d0d61e18a1614f615774c}{PLL3\+RGE}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_r_c_c___p_l_l3_init_type_def_a7e10a2cd67470b69374f84248d11c362}{PLL3\+VCOSEL}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_r_c_c___p_l_l3_init_type_def_a37290cc3566aeeb6f60a6f0f01173bf0}{PLL3\+FRACN}}
\end{DoxyCompactItemize}


\doxysubsection{Detailed Description}
PLL3 Clock structure definition. 

\label{doc-variable-members}
\Hypertarget{struct_r_c_c___p_l_l3_init_type_def_doc-variable-members}
\doxysubsection{Member Data Documentation}
\Hypertarget{struct_r_c_c___p_l_l3_init_type_def_a37290cc3566aeeb6f60a6f0f01173bf0}\index{RCC\_PLL3InitTypeDef@{RCC\_PLL3InitTypeDef}!PLL3FRACN@{PLL3FRACN}}
\index{PLL3FRACN@{PLL3FRACN}!RCC\_PLL3InitTypeDef@{RCC\_PLL3InitTypeDef}}
\doxysubsubsection{\texorpdfstring{PLL3FRACN}{PLL3FRACN}}
{\footnotesize\ttfamily \label{struct_r_c_c___p_l_l3_init_type_def_a37290cc3566aeeb6f60a6f0f01173bf0} 
uint32\+\_\+t RCC\+\_\+\+PLL3\+Init\+Type\+Def\+::\+PLL3\+FRACN}

PLL3\+FRACN\+: Specifies Fractional Part Of The Multiplication Factor for PLL3 VCO It should be a value between 0 and 8191 \Hypertarget{struct_r_c_c___p_l_l3_init_type_def_abf03c908c2a85af8a4e49f9988ad3a33}\index{RCC\_PLL3InitTypeDef@{RCC\_PLL3InitTypeDef}!PLL3M@{PLL3M}}
\index{PLL3M@{PLL3M}!RCC\_PLL3InitTypeDef@{RCC\_PLL3InitTypeDef}}
\doxysubsubsection{\texorpdfstring{PLL3M}{PLL3M}}
{\footnotesize\ttfamily \label{struct_r_c_c___p_l_l3_init_type_def_abf03c908c2a85af8a4e49f9988ad3a33} 
uint32\+\_\+t RCC\+\_\+\+PLL3\+Init\+Type\+Def\+::\+PLL3M}

PLL3M\+: Division factor for PLL3 VCO input clock. This parameter must be a number between Min\+\_\+\+Data = 1 and Max\+\_\+\+Data = 63 \Hypertarget{struct_r_c_c___p_l_l3_init_type_def_a5f97ae4e24ae3b2458e2420e15fc6a28}\index{RCC\_PLL3InitTypeDef@{RCC\_PLL3InitTypeDef}!PLL3N@{PLL3N}}
\index{PLL3N@{PLL3N}!RCC\_PLL3InitTypeDef@{RCC\_PLL3InitTypeDef}}
\doxysubsubsection{\texorpdfstring{PLL3N}{PLL3N}}
{\footnotesize\ttfamily \label{struct_r_c_c___p_l_l3_init_type_def_a5f97ae4e24ae3b2458e2420e15fc6a28} 
uint32\+\_\+t RCC\+\_\+\+PLL3\+Init\+Type\+Def\+::\+PLL3N}

PLL3N\+: Multiplication factor for PLL3 VCO output clock. This parameter must be a number between Min\+\_\+\+Data = 4 and Max\+\_\+\+Data = 512 or between Min\+\_\+\+Data = 8 and Max\+\_\+\+Data = 420(\texorpdfstring{$\ast$}{*}) (\texorpdfstring{$\ast$}{*}) \+: For stm32h7a3xx and stm32h7b3xx family lines. \Hypertarget{struct_r_c_c___p_l_l3_init_type_def_a9a1a667bbc487367b94bb798c51c7ed3}\index{RCC\_PLL3InitTypeDef@{RCC\_PLL3InitTypeDef}!PLL3P@{PLL3P}}
\index{PLL3P@{PLL3P}!RCC\_PLL3InitTypeDef@{RCC\_PLL3InitTypeDef}}
\doxysubsubsection{\texorpdfstring{PLL3P}{PLL3P}}
{\footnotesize\ttfamily \label{struct_r_c_c___p_l_l3_init_type_def_a9a1a667bbc487367b94bb798c51c7ed3} 
uint32\+\_\+t RCC\+\_\+\+PLL3\+Init\+Type\+Def\+::\+PLL3P}

PLL3P\+: Division factor for system clock. This parameter must be a number between Min\+\_\+\+Data = 2 and Max\+\_\+\+Data = 128 odd division factors are not allowed \Hypertarget{struct_r_c_c___p_l_l3_init_type_def_a0b26665402abcaa012598f506e1aeae0}\index{RCC\_PLL3InitTypeDef@{RCC\_PLL3InitTypeDef}!PLL3Q@{PLL3Q}}
\index{PLL3Q@{PLL3Q}!RCC\_PLL3InitTypeDef@{RCC\_PLL3InitTypeDef}}
\doxysubsubsection{\texorpdfstring{PLL3Q}{PLL3Q}}
{\footnotesize\ttfamily \label{struct_r_c_c___p_l_l3_init_type_def_a0b26665402abcaa012598f506e1aeae0} 
uint32\+\_\+t RCC\+\_\+\+PLL3\+Init\+Type\+Def\+::\+PLL3Q}

PLL3Q\+: Division factor for peripheral clocks. This parameter must be a number between Min\+\_\+\+Data = 1 and Max\+\_\+\+Data = 128 \Hypertarget{struct_r_c_c___p_l_l3_init_type_def_aad5f277a07cd7b0c045f336c8818b210}\index{RCC\_PLL3InitTypeDef@{RCC\_PLL3InitTypeDef}!PLL3R@{PLL3R}}
\index{PLL3R@{PLL3R}!RCC\_PLL3InitTypeDef@{RCC\_PLL3InitTypeDef}}
\doxysubsubsection{\texorpdfstring{PLL3R}{PLL3R}}
{\footnotesize\ttfamily \label{struct_r_c_c___p_l_l3_init_type_def_aad5f277a07cd7b0c045f336c8818b210} 
uint32\+\_\+t RCC\+\_\+\+PLL3\+Init\+Type\+Def\+::\+PLL3R}

PLL3R\+: Division factor for peripheral clocks. This parameter must be a number between Min\+\_\+\+Data = 1 and Max\+\_\+\+Data = 128 \Hypertarget{struct_r_c_c___p_l_l3_init_type_def_ab47e853e3c4d0d61e18a1614f615774c}\index{RCC\_PLL3InitTypeDef@{RCC\_PLL3InitTypeDef}!PLL3RGE@{PLL3RGE}}
\index{PLL3RGE@{PLL3RGE}!RCC\_PLL3InitTypeDef@{RCC\_PLL3InitTypeDef}}
\doxysubsubsection{\texorpdfstring{PLL3RGE}{PLL3RGE}}
{\footnotesize\ttfamily \label{struct_r_c_c___p_l_l3_init_type_def_ab47e853e3c4d0d61e18a1614f615774c} 
uint32\+\_\+t RCC\+\_\+\+PLL3\+Init\+Type\+Def\+::\+PLL3\+RGE}

PLL3\+RGE\+: PLL3 clock Input range This parameter must be a value of \doxylink{group___r_c_c___p_l_l3___v_c_i___range}{RCC PLL3 VCI Range} \Hypertarget{struct_r_c_c___p_l_l3_init_type_def_a7e10a2cd67470b69374f84248d11c362}\index{RCC\_PLL3InitTypeDef@{RCC\_PLL3InitTypeDef}!PLL3VCOSEL@{PLL3VCOSEL}}
\index{PLL3VCOSEL@{PLL3VCOSEL}!RCC\_PLL3InitTypeDef@{RCC\_PLL3InitTypeDef}}
\doxysubsubsection{\texorpdfstring{PLL3VCOSEL}{PLL3VCOSEL}}
{\footnotesize\ttfamily \label{struct_r_c_c___p_l_l3_init_type_def_a7e10a2cd67470b69374f84248d11c362} 
uint32\+\_\+t RCC\+\_\+\+PLL3\+Init\+Type\+Def\+::\+PLL3\+VCOSEL}

PLL3\+VCOSEL\+: PLL3 clock Output range This parameter must be a value of \doxylink{group___r_c_c___p_l_l3___v_c_o___range}{RCC PLL3 VCO Range} 

The documentation for this struct was generated from the following file\+:\begin{DoxyCompactItemize}
\item 
C\+:/\+Users/\+ASUS/\+Desktop/dm-\/ctrl\+H7-\/balance-\/9025test/\+Drivers/\+STM32\+H7xx\+\_\+\+HAL\+\_\+\+Driver/\+Inc/\mbox{\hyperlink{stm32h7xx__hal__rcc__ex_8h}{stm32h7xx\+\_\+hal\+\_\+rcc\+\_\+ex.\+h}}\end{DoxyCompactItemize}
